1. Field of the Invention
The present invention relates to picosecond imaging circuit analysis in integrated circuits and, more particularly, to evaluation of latchup, ElectroStatic Discharge (ESD) and power bus robustness in computer chips.
Secondly, this invention relates to an apparatus and a method for a transmission line pulse picosecond imaging circuit analysis tool, and more particularly for characterization of pulsed voltage, current, and photon emissions in computer chips.
Thirdly, the present invention relates to the emulation of PICA (Picosecond Imaging Circuit Analysis) in integrated circuits from electrothermal circuit simulation, and more particularly, to evaluation of high current electrothermal phenomena in computer chips.
It is noted that the time scale for the optical measurement may be picoseconds or any other multiple thereof in accordance with this invention.
2. Description of the Related Art
As electronic components become smaller and smaller along with the internal structures in integrated circuits, the risk of either completely destroying or otherwise impairing electronic components from latchup increases. In particular, many integrated circuits are highly susceptible to latchup damage. Latchup, which involves a high current state leading to destructive or catastrophic damage, is typically understood as initiation of a PNPN structure, or silicon controlled rectifier (SCR) structure. The PNPN structure is intentionally designed, or is the result of a PNPN structure unintentionally formed between structures. Latchup can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit). Latchup has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic. Often the device is weakened only slightly, but is less able to withstand normal operating stresses, and that weakness may result in a reliability problem. Latchup is initiated by an equivalent circuit of a cross-coupled PNP and NPN transistor.
Regenerative feedback occurs between a PNP and an NPN transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second. Such PNP and NPN elements can exist in any diffusions or implanted regions of other circuit elements (e.g. P-channel MOSFETs, N-channel MOSFETs, resistors, etc) or actual PNP and NPN bipolar transistors.
FIG. 1 illustrates a prior art CMOS FET device 7, which comprises a P− doped silicon substrate 18 in which an N−well 8 has been formed. An N+ doped contact region 10 and one of the source/drain P doped diffusion regions 12 are shown formed in the N−well. A P+ doped contact region 16 and one of the source/drain N+ diffusion regions 14 are shown formed in the P− doped substrate 18. The N+ doped contact region 10 is connected by line 10C to power supply voltage VDD and P+ doped contact region 16 is connected by line 16C to reference potential VSS. Line 12C is connected to P+ doped diffusion region 12 and line 14C is connected to the N+ doped diffusion region 14.
For example in a CMOS device, such as the device 7 in FIG. 1, an unwanted, parasitic PNPN structure is formed with a P− diffusion in the N−well 8 in the P− doped substrate 18. In the case of a parasitic PNPN, the N− well region 8 and the substrate region 18 are inherently involved in the latchup current exchange between regions. Latchup triggering conditions are a function of the current gain of the parasitic PNP and parasitic NPN bipolar transistors, and the resistance between the emitter and the base regions of those parasitic bipolar transistors. This inherently involves the N− well 8 and the substrate region 18. The latchup sensitivity is a function of spacings (e.g. base width of the parasitic NPN bipolar transistor and base width of the parasitic PNP bipolar transistor), current gain of the parasitic transistors, substrate resistance and spacings, and the well resistance and spacings. Isolation regions also play a role in the latchup sensitivity of a technology.
Latchup tolerance scaling is a function of the doping concentrations, and scaling characteristics of a technology. A common solution to reduce noise is to lower the well and substrate resistances.
In internal circuits and peripheral circuitry, latchup and noise are both a concern. Latchup and noise are initiated in the substrate from overshoot, and undershoot phenomena. These are generated by CMOS off-chip driver circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate. Hence, both a P− channel MOSFET and N− channel MOSFET can lead to substrate injection. Simultaneous switching of circuitry where overshoot or undershoot injection occurs, leads to injection into the substrate which leads to both noise injection and latchup conditions. Supporting elements in these circuits, such as pass transistors, resistor elements, test functions, overvoltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can lead to injection into the substrate. ESD elements connected to the input pad can also lead to noise injection and latchup. ESD elements that can lead to noise injection, and latchup include MOSFETs, PNPN SCR, ESD structures, P+/N− well diodes, N−well to substrate diodes, N+ diffusion diodes, and other ESD circuits. ESD circuits can contribute to noise injection into the substrate and latchup.
With the growth of the high-speed data rate transmission, optical interconnect, wireless and wired marketplaces, the breadth of mixed signal and radio frequency (RF) applications and requirements is broad. Each type of application space has a wide range of power supply conditions, a number of independent power domains, and circuit performance objectives. Different power domains are established between digital, analog and radio frequency (RF) functional blocks on an integrated chip. With System-On-a-Chip (SOC), different circuit and system functions are integrated into a common chip substrate.
Latchup leads to interaction of the ESD network, the I/O circuit, and the power bus as well as the chip substrate and architecture. Latchup is initiated or triggered by the ESD element, or the I/O circuit. When it occurs, the failure process, temporally, is not observed and it is not clear what is the current path, what is the process of initiation and what are the elements involved. For ESD networks, it is not clear what is the mode of operation and what is the response as the current is increased. Again, in observing ESD failures it is hard to tell after failure of whether the ESD or the I/O circuit failed first. Again, having analysis in a time domain would allow visualization of the failure process.
For RF applications in RF CMOS, BiCMOS, BiCMOS SiGe and analog applications, that become oscillatory as the RF signal increases, failure of the RF circuits and ESD, can destroy elements. With respect to RF signal levels which can destroy circuits, knowledge of the positive or negative oscillation peaks will allow understanding how the RF circuit fails. Using the photon emission evaluation process, an element that is leading to failure can be identified.
For analysis of semiconductor failure mechanisms and evaluation of the optical sources, it is valuable for us to distinguish whether structures are in forward or reverse bias and whether the structures are generating low electric field and high electric fields. This is important for understanding the recombination emissions from those of avalanche phenomena.
High current pulse testing is valuable for evaluation of electronic components under a pulsed mode. For the evaluation of the current and voltage, a system is needed that is capable of capturing the current, and voltage of the component. Hence it is important for a test system to be able to measure the voltage and current to provide an understanding of the voltage and current under pulsed conditions. Measurements of the pulsed voltage and current can provide the terminal currents in a device.
Photons are emitted from the structures. Analysis of the spatial density and time evolution of the photon emission allows for the understanding of how the current distributes in the structure. Photon emissions using a DC voltage source provides a DC method of determining the photon emissions.
PICA (Picosecond Imaging Circuit Analysis) has been previously used to observe the switching activities of CMOS circuits and is described in U.S. Pat. No. 5,940,545 entitled, “Noninvasive Optical Method for Measuring Internal Switching and Other Dynamic Parameters of CMOS Circuits”, and is herein incorporated by reference. A test system and method that can provide the pulsed voltage, current, and PICA for photo emission mapping temporally in space and time will allow for a high current pulse method that is utilized for electronic components.